`include "counter.v"
`include "control.v"
`include "mux.v"
`include "reg.v"
`include "alu.v"

module top(input clk,
           input rstN,
           input [15:0] inst_in,
           output [15:0] bus);

wire [1:0] counter_out;
wire [9:0] mux_ctrl;
wire [9:0] reg_enable;
wire [1:0] alu_ctrl;
wire [15:0] alu_out;

//Registradores:
wire [15:0] r0_out;
wire [15:0] r1_out;
wire [15:0] r2_out;
wire [15:0] r3_out;
wire [15:0] r4_out;
wire [15:0] r5_out;
wire [15:0] r6_out;
wire [15:0] r7_out;
wire [15:0] A_out;
wire [15:0] R_out;
register r0(clk, reg_enable[0], mux_out, r0_out);
register r1(clk, reg_enable[1], mux_out, r1_out);
register r2(clk, reg_enable[2], mux_out, r2_out);
register r3(clk, reg_enable[3], mux_out, r3_out);
register r4(clk, reg_enable[4], mux_out, r4_out);
register r5(clk, reg_enable[5], mux_out, r5_out);
register r6(clk, reg_enable[6], mux_out, r6_out);
register r7(clk, reg_enable[7], mux_out, r7_out);
register A(clk, reg_enable[8], mux_out, A_out);
register R(clk, reg_enable[9], alu_out, R_out);

wire [15:0] mux_out;
wire [15:0] immediate; //inst_in[9:0] extended.

assign immediate = {{6{inst_in[9]}}, inst_in[9:0]};

//Instanciacoes de modulo:
mux m(r0_out, r1_out, r2_out, r3_out, r4_out, r5_out, r6_out, r7_out, immediate, R_out, mux_ctrl, mux_out);
control ctrl(rstN, inst_in[15:7], counter_out, clear, mux_ctrl, reg_enable, alu_ctrl);
counter c(clk, rstN, counter_out); 
alu a(A_out, mux_out, alu_ctrl, alu_out);

assign bus = mux_out;

endmodule
